eess.SP
DIY EEG signal acquisition and analysis on a microcontroller
How to wire up an EEG front-end to an ESP32 or Raspberry Pi, filter the signal, and extract band power, coherence, and wavelet entropy in real time.
2026-08-12
Electronics News
Latest research from arXiv, written for makers and embedded engineers.
cs.AI
AgRefactor Uses AI Agents to Turn Ordinary C++ Into FPGA-Ready HLS Code
AgRefactor is an open-source multi-agent AI tool that automatically rewrites software code into synthesizable HLS designs, beating state-of-the-art tools on real-world benchmarks.
2026-08-12
eess.SP
Build a Laser Diode LiFi Link with a Holographic Diffuser
How to build a laser diode LiFi optical wireless link: diffuser optics, IM/DD receiver circuit, bandwidth limits, range vs beamwidth trade-offs explained.
2026-08-12
eess.SY
Wide-band dual-pol microstrip antenna on FR4 at 5.7 GHz
How to get ~10% bandwidth and 40 dB port isolation from a dual-polarized FR4 microstrip patch at 5.7 GHz using topology optimization techniques.
2026-08-08
cs.ET
SpiNNaker2: The Many-Core Chip Bridging Neuromorphic and Deep Learning Worlds
SpiNNaker2 packs 152 ARM cores with custom accelerators onto one chip, hitting 4.5 TOPS while spiking over 150,000 neurons. Here's what that means for edge AI builders.
2026-08-02
cs.AR
DICE Brings Realistic Chiplet Link Simulation to gem5, Fixing a Hidden Accuracy Problem
Researchers built DICE, a runtime PHY model for gem5 that simulates real chiplet interconnect behavior including noise, error correction, and retransmissions.
2026-07-31
physics.ins-det
APEIRON: A Multi-FPGA Framework Built for Physics Experiments That Embedded Engineers Should Know About
APEIRON is a full-stack multi-FPGA framework spanning device drivers to high-level dataflow programming, built for real-time physics data acquisition.
2026-07-22
eess.SP
Rydberg Atom Receivers Use Satellite Doppler Shift as a Built-In Local Oscillator
Researchers show that Rydberg atomic receivers can exploit natural Doppler shifts from moving satellites to replace traditional local oscillator hardware.
2026-07-13
cs.AR
Weave Converts SPICE Netlists to Schematics With 100% Verified Accuracy
Weave is a deterministic tool that converts SPICE netlists into LTspice schematics and mathematically certifies every result is electrically correct.
2026-07-12
cs.AR
ArchEval: How Well Can AI Agents Actually Design Computer Hardware?
A new benchmark called ArchEval tests LLM agents on real hardware design tasks. Results show AI is a useful assistant, not an autonomous architect.
2026-07-12
cs.AR
AIGOR: One FPGA Neuromorphic Architecture That Runs Any Spiking Neural Network
Researchers built AIGOR, a configurable neuromorphic architecture for FPGAs that runs spiking neural networks without locking you into a fixed neuron model or network topology.
2026-07-08
cs.AR
NEMESIS Uses LLMs to Generate Fast, SPICE-Verified Amplifier Equations
A new framework called NEMESIS combines LLMs with SPICE simulation to generate accurate amplifier models that run over 4000x faster than full SPICE.
2026-07-08
eess.SP
FFT as a Neural Network Preconditioner: How Fourier Transforms Improve Feature Learning With Less Data
Researchers show that applying an FFT before training a feature extraction network can cut prediction error by up to 50% in low-data, resource-constrained settings.
2026-07-05
cs.ET
Memristive Memory: What Engineers Need to Know About ReRAM and STT-RAM Reliability
Memristors promise denser, lower-power memory than SRAM, but reliability threats stand in the way. Here is what embedded engineers need to understand.
2026-07-05
cs.AR
Apple M4 Pro's Hidden GPU Cache Hangover: What It Means for Embedded and FPGA Developers
Researchers found that after a GPU command finishes on Apple M4 Pro, leftover cache displacement measurably slows the CPU. Here's what that means for builders.
2026-07-02
cs.AR
Inside Apple's Neural Engine: A Reverse-Engineered Guide for Embedded AI Builders
A detailed reverse-engineered breakdown of Apple's Neural Engine reveals the hardware, firmware, and dispatch paths that Core ML hides from developers.
2026-07-02
cs.CR
Fingerprinting Cloud GPUs Without Root Access: New Attestation Method Verifies Hardware Identity
Researchers built a software-only method to verify which GPU you're actually running on in the cloud, using latency measurements and network probes.
2026-06-25
cs.DC
Four Decades of Parallel Hardware: What Exascale Computing Teaches Embedded Engineers About Synchronization
A new survey traces how hardware synchronization primitives evolved from the NYU Ultracomputer to modern GPU clusters, with lessons relevant to any multi-core embedded design.
2026-06-20
cs.AR
DataGuard: Hardware-Level Privacy Guarantees for On-Device AI Training
DataGuard embeds differential privacy enforcement directly into AI accelerator hardware, removing the need to trust third-party software with sensitive training data.
2026-06-19
cs.LG
HAMON: Could Optical Light Diffraction Replace Digital Math for Time-Series Forecasting?
HAMON encodes time-series data onto light and uses diffractive optics to compute forecasts passively, outperforming digital models on several benchmarks.
2026-06-17
cs.AR
TreeGRNG: A Smarter Way to Generate Gaussian Random Numbers for AI at the Edge
A new binary tree approach to Gaussian random number generation cuts energy by 3.7x and boosts throughput density by 5.8x, making Bayesian Neural Networks practical on ultra-low-power hardware.
2026-06-16
cs.AR
Delta-Aware Training Cuts Neural Network Weight Storage Nearly in Half on Tiny FPGAs
A new compression technique stores neural network weights as small deltas instead of full values, cutting memory use by nearly 50% on resource-constrained FPGAs.
2026-06-16